ICS904/EN2

Digital Integrated CMOS Circuits: design, automation, technology evolution

 

Year 2016 Timetable
Date slot location and room speaker nature contents Comments

Thursday, September 29, 2016
 
 from 1.30 p.m. to 4.45 p.m.

 Telecom ParisTech  / A507 (1)

 Yves MATHIEU  lecture
  • CMOS technology,
  • Bases of CMOS logic
  • MOS switches efficiency
  • CMOS logic efficiency 
  • Moore's laws

Lecture 1 / Slides 

WARNING : do not print slides because animated slides will generate tens of unnecessary pages...

Lecture 1/ Handout (may be printed)

Thursday, October 06, 2016

 from 1.30 p.m. to 4.45 p.m. Telecom ParisTech / A507 Yves MATHIEU   lecture
  • CMOS Logic families (1):
    • MOS complementary logic
    • Pass Transistor logic

Lecture 2 / Slides

WARNING : do not print slides because animated slides will generate tens of unnecessary pages...

Lecture 2/ Handout

Thursday October 13, 2016 from 1.30 p.m. to 4.45 p.m. Telecom ParisTech / A507 Yves MATHIEU lecture/tutorials
  • CMOS Logic families (2):
    • Dynamic logic
    • Differential logic
  • Gate sizing: the buffer optimization exemple
  • Sequential gates
  • Principles of standard-cell design

Lecture 3 / Slides

Lecture 3 / Handout

Home work: 
Study of the operation of a dynamic D flip-flop.

Thursday October 20, 2016

from 1.30 p.m. to 4.45 p.m.
 

Telecom ParisTech / A507
 

Hervé PETIT

practical work
 

Project : design and optimization of a digital standard-cell : layout 
 

 Students have to write a report on the work done during the full project.


 
Thursday 0ctober 27, 2016

from 1.30 p.m. to 4.45 p.m.
 

Telecom ParisTech / A507
 

Yves MATHIEU
 

lecture/tutorials

Standard Cell Libraries : Design for speed, Design for low power (static power  versus dynamic power),

Design for test and testability

Electronic Design Automation: the place and route flow.

Standard Cell Chararcterization: the "Liberty" files.

Lecture 4 / Slides

Lecture 5 / Slides

Lecture 4 / Handout

Lecture 5 / Handout

Thursday November 03, 2016 from 1.30 p.m. to 4.45 p.m. Telecom ParisTech / A507 Hervé PETIT, Yves MATHIEU practical work Project : design and optimisation of a digital standard-cell : characterization  See downloadable files at the bottom of the page
Thursday November 10, 2016 from 1.30 p.m. to 4.45 p.m. Telecom ParisTech / A507

Hervé PETIT, Yves MATHIEU

practical work Project : design and optimisation of a digital standard-cell : characterization  
Thursday November 17, 2016 from 1.30 p.m. to 4.45 p.m. Telecom ParisTech / A507

Hervé PETIT, Yves MATHIEU

practical work
  • Project : design and optimisation of a digital standard-cell : optimization
 
Thursday November 24, 2016 from 1.30 p.m. to 4.45 p.m. C2N Orsay, Salle 322 (2)

Damien QUERLIOZ

 lecture

 

Impact of technology evolution: FinFET, FDSOI, nanotechnology
Design for reliability
Better Than Worst-Case Design

 
Thursday December 08, 2016 from 1.30 p.m. to 3.0 p.m. Telecom ParisTech / A507

Yves MATHIEU

exam  Final exam (quiz)  
Thursday December 08,2016 from 3.15 p.m. to 4.45 p.m. Telecom ParisTech / A507

Hervé PETIT, Yves MATHIEU

 practical work Project : design and optimisation of a digital standard-cell : integration  
 Thursday December 15, 2016   - - - - -  Final Report Due at 11:59 pm

(1) Telecom-Paristech, 46, rue Barraultt, 75013 Paris.

(2) Centre de NanoSciences et de Nanotechnologies, Université Paris-Sud, Bat 220, 91405 Orsay Cedex, France

Fichier attachéTaille
Fichier invx1_fall_transition.tgz6.84 Ko
Fichier tspcff_functional_check.tgz3.4 Ko