ICS904/EN2

Structural Design if Digital Integrated Circuits

 

Year 2017 Timetable
Date slot location and room speaker nature contents Comments

Thursday, October 5, 2017
 
 from 1.45 p.m. to 5.00 p.m.

 Telecom ParisTech  / A405 (1)

 Yves MATHIEU  lecture
  • CMOS technology,
  • Bases of CMOS logic
  • MOS switches efficiency
  • CMOS logic efficiency 
  • Moore's laws

Lecture 1 / Slides 

WARNING : do not print slides because animated slides will generate tens of unnecessary pages...

Lecture 1/ Handout (may be printed)

Thursday, October 12, 2017

from 1.45 p.m. to 5.00 p.m. Telecom ParisTech / A405 Yves MATHIEU   lecture
  • CMOS Logic families (1):
    • MOS complementary logic
    • Pass Transistor logic

Lecture 2 / Slides

WARNING : do not print slides because animated slides will generate tens of unnecessary pages...

Lecture 2/ Handout

Thursday October 19, 2017 from 1.45 p.m. to 5.00 p.m. Telecom ParisTech / A405 Yves MATHIEU lecture/tutorials
  • CMOS Logic families (2):
    • Dynamic logic
    • Differential logic
  • Gate sizing: the buffer optimization exemple
  • Sequential gates
  • Principles of standard-cell design

Lecture 3 / Slides

Lecture 3 / Handout

Home work: 
Study of the operation of a dynamic D flip-flop.

Thursday 0ctober 26, 2017

from 1.45 p.m. to 5.00 p.m.

Telecom ParisTech / A405
 

Yves MATHIEU
 

lecture/tutorials

Standard Cell Libraries : Design for speed, Design for low power (static power  versus dynamic power),

Design for test and testability

Electronic Design Automation: the place and route flow.

Standard Cell Chararcterization: the "Liberty" files.

Lecture 4 / Slides

Lecture 5 / Slides

Lecture 4 / Handout

Lecture 5 / Handout

Thursday November 02, 2017 from 1.45 p.m. to 5.00 p.m. Telecom ParisTech / A505-A507
 
Yves MATHIEU, Chadi JABBOUR practical work Project : design and optimization of a digital standard-cell : layout  Students have to write a report on the work done during the full project.
Thursday November 09, 2017 from 1.45 p.m. to 5.00 p.m.

Telecom ParisTech / A505-A507

Yves MATHIEU, Chadi JABBOUR practical work Project : design and optimisation of a digital standard-cell : characterization  See downloadable files at the bottom of the page
Thursday November 16, 2017 from 1.45 p.m. to 5.00 p.m. C2N Orsay

Damien QUERLIOZ

lecture Impact of technology evolution: FinFET, FDSOI, nanotechnology
Design for reliability
Better Than Worst-Case Design
 
Thursday November 23, 2017 from 1.45 p.m. to 5.00 p.m. Telecom ParisTech / A505-A507

Yves MATHIEU, Chadi JABBOUR

practical work

Project : design and optimisation of a digital standard-cell : characterization

 
Thursday November 30, 2017 from 1.45 p.m. to 5.00 p.m.

Telecom ParisTech / A505-A507

Yves MATHIEU, Chadi JABBOUR

 practical work

Project : design and optimisation of a digital standard-cell : optimization

 
Thursday December 14, 2017 from 1.45 p.m. to 3.15 p.m.

Telecom ParisTech / A505-A507

Yves MATHIEU

exam  Final exam (quiz)  
Thursday December 14, 2017 from 3.30 p.m. to 5.00 p.m.

Telecom ParisTech / A505-A507

Yves MATHIEU, Chadi JABBOUR

 practical work Project : design and optimisation of a digital standard-cell : integration  
 Sunday January 7, 2018   - - - - -  Final Report Due at 11:59 pm

(1) Telecom-Paristech, 46, rue Barraultt, 75013 Paris.

(2) Centre de NanoSciences et de Nanotechnologies, Université Paris-Sud, Bat 220, 91405 Orsay Cedex, France

Fichier attachéTaille
Fichier invx1_fall_transition.tgz6.84 Ko
Fichier tspcff_functional_check.tgz3.4 Ko